1. Field of the Invention
The present invention relates generally to the field of inductors, and more particularly to embedded multi-layer inductors formed in a low temperature, co-fired ceramic (LTCC) substrate.
2. Description of the Related Art
Conventionally, electronic circuit components, including silicon chips, have been mounted on printed circuit boards. More recently, in order to reduce the size associated with conventional printed circuit boards, low temperature, co-fired ceramic (LTCC) substrates have been used.
A typical LTCC configuration comprises multiple layers of ceramic xe2x80x9ctapexe2x80x9d which are used to provide the base structure upon which to form various electronic components and electrical connections. The tape is formed from a powdered ceramic, mixed with a binder. For example, one type of ceramic tape available from Dupont is known as xe2x80x9cGreen Tape 951.xe2x80x9d The electronic components that can be formed include resistors, capacitors, inductors, and the like. The electrical connections, formed through each tape layer, are known as xe2x80x9cvias.xe2x80x9d The components are formed by punching holes/vias in the tape as appropriate, and layering on metal, dielectrics, insulators, etc. Several layers of tape may be used in order to form the desired circuitry. The tape layers are then pressed together and fired in an oven to remove the binder and to sinter the ceramic powder. Components which are too large or too difficult to form within the ceramic tape layers, such as silicon chip capacitors, resistors, inductors, and chips, may be surface mounted on the hardened substrate. The resulting substrate is usually less than 1xe2x80x3xc3x971xe2x80x3, thus providing a compact circuit package.
FIG. 1 shows an example of the structure of a basic capacitor 10 formed within an LTCC substrate. A standard process to form this structure will now be described, with reference to FIG. 1. First, a hole is punched in a first tape layer 12 to form an opening. A silver, silver palladium, or similar paste is wiped across the hole to form a via 16, which is used as one terminal connection for the capacitor 10. Next, a first electrode 18 may be formed on top of the via 16 using silver, silver palladium or other similar electrode paste. After the electrode 18 has dried, a dielectric 20 is formed on top of the electrode 18. A dielectric paste is usually used, which when hardened, provides the desired dielectric properties. A second electrode 22 is then formed on top of the dielectric layer 20. These various component layers are commonly formed using a screen printing process. A second ceramic tape layer 14 having a via 24 is then pressed on top of the first layer 12. The second via 24 provides a second terminal for the capacitor 10. After the substrate is fired at 750-950xc2x0 C., a capacitor structure 30 is formed as shown in FIG. 2. A top view of the capacitor structure 30 is shown in FIG. 3. The vias can have cross-sectional shapes of circles, squares, or rectangles.
This procedure forms what is known in the art as a single layer ceramic capacitor (SLCC), also known as a mono-layer capacitor. Another embodiment of an SLCC is shown in FIG. 4. Specifically, the vias 42, 44 may be formed on the side of the electrodes 46,48, or with one via 42 in the middle of one electrode 46, and one via 44 on the side of the other electrode 48. The electrodes and dielectrics may also be formed as circles, squares or rectangles as shown in FIGS. 5(A)-5(C).
For standard capacitor configurations, the capacitance of a structure is determined according to the following formula:
C=(kA)/t,
where k is the dielectric constant of the dielectric material, A is the overlapping area between the electrodes, and t is the thickness of the dielectric, as shown in FIG. 7. Note that in FIG. 7, the dielectric area A and the electrode area A are presumed to be the same, but in practice the dielectric is usually made larger to ensure that the electrode layers do not touch. Thus, by changing the dielectric material, the capacitance value may be changed. FIG. 6 illustrates an SLCC in which a different dielectric is used, in order to change the capacitance. Instead of using a dielectric paste, the dielectric may be formed from a high firing temperature ceramic tape (1100-1400xc2x0 C.). The high temperature tape 66 is fired separately, and then placed on the first electrode 72. The dielectric constant of the high temperature tape 66 is several orders of magnitude greater (k=20xe2x88x9220,000) than the dielectric constant of the standard tape (k=7-8) used to form the layers 62, 64. Standard tape 68,70 may be used around the dielectric to provide a constant thickness between the main layers 62, 64.
Two articles which discuss LTCC technology include xe2x80x9cCharacterization and Performance Prediction for Integral Capacitors in Low Temperature Co-Fired Ceramic Technology,xe2x80x9d Delaney et al., IEEE Transactions on Advanced Packaging, Vol. 22, No. 1, February 1999, pgs. 68-77; and xe2x80x9cCharacteristics of the Electrical Performance of Buried Capacitors and Resistors in Low Temperature Co-Fired (LTCC) Ceramic,xe2x80x9d Delaney et al., 1998 Electronic Components and Technology Conferences, pgs. 900-908, the disclosures of which are herein incorporated by reference. While these articles seek to address the problem of providing capacitors with increased capacitance, the capacitors are still confined to being formed within a single layer of ceramic tape. The disclosed processes cannot make high capacitance capacitors and they require numerous types of dielectric materials in order to create different capacitances.
Since there is a practical limit to the dielectric constant that can be achieved, single layer capacitors do not provide sufficient capacitance within a reasonable area, for many applications. Thus, for high value capacitances, external capacitors are often surface mounted on the ceramic substrate. An example of one type of capacitor 8000 used for this purpose is shown in FIG. 8. Multiple layers of electrodes are formed in a discrete ceramic capacitor, and are used in order to increase the capacitance, while still providing a relatively small component. Adding external components, however, increases the costs associated with the LTCC circuit.
The articles xe2x80x9cManufacture of Embedded Integrated Passive Components into Low Temperature Co-Fired Ceramic Systems,xe2x80x9d Scrantom et al., 1998 International Symposium on Microelectronics, 1998, pp. 459-466, xe2x80x9c3D-Integration of Passive RF-Components in LTCC,xe2x80x9d Muller et al., and xe2x80x9cIntegrated Passive Components Using Low Temperature Cofired Ceramics,xe2x80x9d Wersing et al., 1998 International Symposium on Microelectronics, 1998, pp. 193-199, discuss the embedding inductors in co-fired ceramics.
FIG. 18 is an end view of an LTCC planar inductor that may be used in the prior art. In this example, planar inductor 1804 is placed between a first tape layer 1808 and a second tape layer 1812. FIG. 19 is a top cross-sectional view of FIG. 18 along cut lines 19xe2x80x9419. The planar inductor 1804 is in a single plane, but has a serpentine or meandering shape, as shown. The serpentine shape provides a low inductance inductor in a single plane.
FIG. 20 is a side view of an LTCC three dimensional inductor that may be used in the prior art. In this example, a first ceramic tape layer 2004, a second ceramic tape layer 2008, a third ceramic tape layer 2012, and a fourth ceramic tape layer 2016 are provided. Between the first and second tape layers 2004, 2008, a first inductor ring 2020 is provided. A second inductor ring 2024 may be placed between the second and third tape layers 2008, 2012. A third inductor ring 2028 may be placed between the third and fourth tape layers 2012, 2016. The first, second, and third inductor rings 2020, 2024, 2028 are embedded and therefore are shown with broken lines. FIG. 21 is a cross-sectional view of the LTCC three-dimensional inductor shown in FIG. 20 along cut lines 21xe2x80x9421, which shows a cross-sectional view of the second tape layer 2008 and the second inductor ring 2024. The second inductor ring 2024 forms an almost complete ring with a first end and a second end. A first via pad 2104 is at a first end of the second inductor ring 2024. A second via pad 2108 is at a second end of the second inductor ring 2024. Similarly, the first inductor ring 2020 and the third inductor ring 2028 may have first and second ends. A first electrode 2032 may be electrically connected to the first end of the first inductor ring 2020. A first via 2036 may be electrically connected between the second end of the first inductor ring 2020 and a first via pad 2104. A second via 2040 may be electrically connected between the second via pad 2108 and the first end of the third inductor ring 2028. A second electrode 2044 may be electrically connected to the second end of the third inductor ring 2028. As can be seen in FIG. 21, the second electrode 2044 passes through the hole in the second inductor ring 2024. The resulting inductor provides about three turns over about three or four ceramic tape layers.
Higher, more compact inductors may be surface mounted on the ceramic substrate.
It would thus be desirable to have a 3-D embedded inductor that is thinner than the prior art. Such thinner inductors are more compact, taking up less landscape and may provide higher inductance.
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques for forming an embedded three-dimensional inductor is provided. Generally, a first coil winding is formed. A first dielectric layer is placed on the first coil winding. At least part of second coil winding is formed on the first dielectric layer and part of the first coil winding to create an electrical contact between the first coil winding and the second coil winding. A first tape layer with a cavity is provided, where the first coil winding, the first dielectric layer, and the second coil winding are within the cavity of the first tape layer.
In addition, an embedded three-dimensional inductor in a low temperature, co-fired ceramic (LTCC) substrate is provided. Generally, a tape layer with a cavity is provided. An inductor coil is within the cavity, where the inductor coil comprises a first winding and at least part of a second winding spaced vertically apart from the first winding. A dielectric layer is within the cavity between the first winding and the at least part of the second winding.
Thus, the present invention is not limited to any specific configuration or geometry of openings or vias, but the teachings encompass any structure having exposed vias connected to the edges of alternating layers of electrodes, in order to provide electrical connectivity.